Field of the Invention
The present invention relates to a semiconductor device and a power converter, and more particularly to a power semiconductor device and a power converter using the power semiconductor device.
Description of the Background Art
For an insulated gate bipolar transistor (IGBT) applied as a switching device in a power converter, a high breakdown voltage, low power loss, and satisfactory switching characteristics are required.
According to Japanese Patent Application Laid-Open No. 2005-56912, a trench gate structure is disclosed as a gate structure of a transistor. The thickness of an insulation film on a side wall of a trench is set to be larger than the thickness of the insulation film on a bottom portion of the trench. According to Japanese Patent Application Laid-Open No. 2005-56912 above, owing to the structure, it is assumed that a breakdown voltage can be maintained to be high even when a trench is deeply formed.
One IGBT disclosed in Japanese Patent Application Laid-Open No. 2016-115847 has a p-type embedded region in a bottom portion of a trench formed in an n-type drift layer. Further, another IGBT disclosed in Japanese Patent Application Laid-Open No. 2016-115847 has a p-type column region between adjacent trenches formed in an n-type drift layer. The above-mentioned p-type embedded region or p-type column region may contribute to enhancement in breakdown voltage through alleviation of electric field concentration.
Power loss of an IGBT is roughly divided into on-steady loss and switching loss. The on-steady loss is proportional to a saturation voltage in the on state, that is, an on-voltage. Therefore, the on-steady loss can be reduced by suppressing the on-voltage. For a switching operation, a high speed in switching and suppression in an oscillation phenomenon and a snap-off phenomenon are required as well as lowness in switching loss. As a method of enhancing switching characteristics, there is known a method of reducing impurity concentration in a collector region to suppress carrier concentration on the collector side. However, suppression in carrier concentration involves adverse influence of increase in on-voltage. The on-voltage can be suppressed through reduction in thickness of a drift layer. However, in view of securing a breakdown voltage and a safety operating area (SOA), application of the method of excessively reducing the thickness of the drift layer is limited.
According to Japanese Patent Application Laid-Open No. 2016-157934, there is disclosed a trench gate IGBT that is intended to suppress reduction in switching controllability along with reduction in on-voltage. This IGBT has a carrier storage layer for reducing the on-voltage. The carrier storage layer is a high-concentration impurity layer of a first conductivity type that is formed on a drift layer of a first conductivity type. The carrier storage layer has a peak position where its impurity concentration is the highest. The thickness of a gate insulation film on a side surface of a trench is set to be larger on the collector layer side with respect to the above-mentioned peak position than on the opening side of the trench with respect to the above-mentioned peak position. According to Japanese Patent Application Laid-Open No. 2016-157934, even when carriers are stored in the vicinity of the side surface of the trench positioned near the carrier storage layer at the time of transition from the off state to the on state, such a thick gate insulation film is formed in at least a part of the side surface of the trench. Therefore, it is assumed that change in gate potential due to the carriers can be suppressed in the portion having the thick gate insulation film and that reduction in switching controllability can be thereby suppressed.
The above-mentioned p-type embedded region that is expected to be effective for enhancement in breakdown voltage may impair the on-voltage reducing effect obtained by the above-mentioned carrier storage layer. This is because electron injection from the carrier storage layer into the drift layer along the side wall of the trench is inhibited by the p-type embedded region. Reduction in efficiency of electron injection into the drift layer suppresses increase in hole concentration corresponding to the electron injection. Therefore, carrier concentration in the drift layer is reduced, thus increasing the on-voltage. In a case where the above-mentioned p-type column region that is expected to be effective for enhancement in breakdown voltage is provided, the carrier storage layer cannot be widely formed in a manner of connecting adjacent trenches in the in-plane direction. As a result, in a potential barrier formed in the interface of the carrier storage layer and the drift layer, the storage amount of holes injected from the collector side is reduced. As a result, carrier concentration in the drift layer is reduced, thus increasing the on-voltage. As described above, there usually is a tradeoff relationship between enhancement in the breakdown voltage and suppression in the on-voltage.
In a case where the thickness of the gate insulation film on the side surface of the trench is set to be larger in a portion on the collector layer side with respect to the above-mentioned peak position with the intention of suppressing reduction in switching controllability, capacitance formed by a gate electrode and a semiconductor region that are opposed to each other with intermediation of the portion is reduced, and therefore electrons stored in the vicinity of the portion are reduced. As a result, efficiency of electron injection into the drift layer is reduced, and hence increase in hole concentration corresponding to the electron injection is suppressed. Therefore, carrier concentration in the drift layer is reduced, thus increasing the on-voltage.